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查了2篇资料,MCLK貌似不是必须的:
https://en.wikipedia.org/wiki/I%C2%B2S
The bus consists of at least three lines:
Bit clock line
Word clock line - also called word select (WS) or left right clock (LRCLK)
At least one multiplexed data line
It may also include the following lines:
Master clock (typical 256 x LRCLK)
A multiplexed data line for upload
http://www.planetanalog.com/document.asp?doc_id=528195
Typically, DSPs don't require an audio master clock